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ApplicationEngineer

Job Description and Requirements
You will be part of an expert product engineering team working on physical verification support for a strategic customer in Synopsys Design Group. Your role as a specialist in physical verification EDA tools will be:
Understand the latest requirements for physical design and verification on advanced technology nodes (16nm and below).
Provide technical support during the installation, implementation, and maintenance of Synopsys IC Validator and related products.
Analyze customer data, pin-point issues, implement the optimizations by working closely with software development teams.
Deploy the advanced features in the latest release of the software to get optimum performance and accuracy on customer designs.
Strong presentation skills
You will directly interact with several groups, including Synopsys software development and marketing teams, support engineers in the field, and the customer. You will be expected to work both independently and in teams to creatively resolve a wide range of issues. You will regularly represent the organization on business unit and/or company-wide projects.
Key Qualifications
We are seeking self-motivated engineers and technologists who excel in solving "bleeding-edge" physical design and verification challenges. If you are excited by an opportunity to apply knowledge in technology areas such as FinFET cell design, runset optimization, semiconductor manufacturing, python scripting and machine learning to resolve problems, this role is for you.
In addition, we are looking for:
Required Skills
An understanding of the design process and knowledge of the ASIC design flow, VLSI, and/or CAD engineering
Strong communication skills
Basic programming/scripting experience with standard languages such as TCL/Perl/Python
Familiarity with principles of foundry processes and manufacturing requirements
Knowledge of the typical hierarchical ASIC place and route and flow
Desired Skills
Experience in foundry runset creation (for DRC/LVS/ERC/DFM), solving LVS issues, knowledge of foundry processes, or understanding advanced DFM requirements
Proficiency with IC Validator or similar physical verification tools such as Calibre, Assura, PVS or Quartz.
Experience with IC Compiler or other place and route tools.
Experience with Custom Compiler or other custom layout tools.
Familiarity with chip-finishing issues (metal-fill, DFM rules, litho simulation, etc.) for advanced process technologies



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