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Compiler Intern

Job Description and Requirements
Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything?where devices are getting smarter, everything's connected, and everything must be secure.
Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world's most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.
The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP Prototyping Kits and IP subsystems. Our extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
This internship with be with our Solutions IP group and is for an immediate start at 40 hours/week.
We are looking for a student to work on a highly optimizing C/C++ compilers that produce fast and tight code to help customers develop embedded applications. MetaWare software development toolchain for the Synopsys' DesignWare? ARC? family of processors is used in a variety of market segments such as internet of things, automotive, industrial, storage, communication, mobile, and digital home; by over 225 customers worldwide who collectively ship more than 2 billion chips annually.
https://www.synopsys.com/designware-ip/processor-solutions/arc-processors.html
Key Responsibilities:
Enhance commercial C/C++ compiler and software development toolchain
Specifically to develop the code generator for a new 64-bit ISA
Develop experimental analysis, optimization and code generation passes
Enhance compiler benchmarking and testing harness
Skill Requirements:
Good C/C++ programming language
Good understanding of data structures and algorithms
Basic understanding of compilers and toolchains
Basic scripting (Python/Perl and Unix bash)
Motivated to learn LLVM
The following qualifications are a plus:
LLVM compiler (or GCC, CoSy) familiarity
Knowledge of RISC and DSP processor architectures and assembler languages
Good understanding of machine learning techniques
Ability to localize and fix problems in an embedded test environment setup
Technical English (writing reports, documentation, email communications)
Education Requirements:
Must be currently enrolled in a Bachelors, Masters or PhD Program or no more than 6 months post graduation



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